Dr. J.S.Y. Jeedella


Role in PROUD committee: Member

Dr. J.S.Y. Jeedella received his Ph.D. in Electronic Engineering from the University of Bradford, UK in 2008 and his MSc in electronics from Eindhoven University of Technology, NL, 1995. From 1993-1995, he was research assistant in Delft University of Technology where he received his MSc in information technology.

From 1995-2004 he was working in Philips Consumer Electronics, Eindhoven, NL where he worked on a variety of electronic and information processing systems. From 2008 -2012 he worked as Senior lecturer in the electronic department within Khalifa University of Sciences, Technology and Research. He taught several courses among others embedded systems, digital design, and basic electric circuits. He also conducted research in the field of transient analysis of Infinite Impulse Response (IIR) digital filters, Smart Homes, Indoor Navigation Systems. and Image Watermarking

Currently he is working as Senior lecturer in the electrical and electronic department within Fontys University of Applied Sciences. His current research interests include digital signal processing, image processing, Computer Vision, information hiding, Wireless networks, embedded systems, and reconfigurable systems.